This invention pertains to a method and apparatus for providing a stable output signal, and more particularly to a method and apparatus for providing a stable output signal with significantly reduced noise and ripple without the use of Tantalum or other types of capacitors having relatively large equivalent series resistance.
Many electrical and electronic circuits, including voltage regulators such as switching regulators, implement an output stage to stabilize a generated output signal supplied to a load by reducing the amount of noise and ripple in the output signal. In an attempt to stabilize the output voltage across the load, the output stage of most switching regulators employ a network of inductive and capacitive energy storage elements which attempt to provide a continuous, stable and regulated output voltage. FIG. 1 depicts an output stage 120 of a voltage regulator comprising an inductor L1, and a capacitor C1 having an equivalent series resistance (ESR) Resr.
Regulated power systems, such as switching regulators, employ negative feedback and various sampling techniques to maintain output voltage or current regulation. These feedback systems need to maintain a sufficient phase margin, for example 35xc2x0, to ensure stability. If a sufficient phase margin is not maintained the output regulation is negatively impacted with unacceptable oscillations.
The stability of the output signal 126 is significantly affected by the poles and zeros introduced by output stage 120. A first pole P1 results from the cooperation of the inductor L1 and capacitor C1 is introduced by output stage 120 at a first pole frequency fP1, approximated by:
fp1=1/(2xcfx80*sqrt(L1*C1)).xe2x80x83xe2x80x83Eq. 1 
Output stage 120 also generates a zero Z1 at a zero frequency fz1 which is approximated by:
fz1=1/(2xcfx80*C1*Resr)xe2x80x83xe2x80x83Eq. 2 
As can be seen from equation 2, the ESR resistance of output capacitor C1 affects the resulting zero frequency fz1. Because of this ESR effect on the zero frequency fz1, capacitors having relatively high ESR resistance are utilized for output capacitor C1 to provide a zero Z1 at a zero frequency fz1 which will maintain a phase margin at a sufficient level to achieve the desired stable output signal 126.
Pole frequency fp1 defined by equation 1 is substantially equal for most capacitors utilized, whether a Tantalum, aluminum electrolytic, ceramic or other capacitor is used, assuming their capacitance is approximately equal. However, because the ESR is different for different types of capacitors, the zero frequency fz1 for zero Z1 will not be equal for different types of capacitors. For example, because of the relatively large difference in ESR resistance between ceramic and Tantalum capacitors, there is a relatively large difference in the zero frequencies fz1. Typically, the ESR resistance associated with a Tantalum capacitor is in the order of 10 to 40 times the ESR resistance of the ceramic capacitor for substantially equivalent capacitive values. This large difference in ESR resistance results in a relatively large difference in the zero frequency fz1 as defined by equation 2.
FIGS. 2A and 2B show Bode plots of the response of output stage 120, where a Tantalum capacitor is employed for capacitance C1. The Bode plot of FIG. 2A depicts the gain 122 versus frequency, and FIG. 2B depicts the phase 123 versus frequency. It is shown that there is an initial drop of both gain 122 and phase 123 which is caused by pole P1 at pole frequency fp1. Referring to FIG. 2B, as phase 123 shifts towards xe2x88x92180xc2x0, the phase margin 125 decreases. If the phase margin 125 drops below a predefined margin (for example 35xc2x0) the output signal 126 starts to become less stable as oscillation, noise and ripple become more apparent in output signal 126. However, phase 123 begins to shift up at reference 128 and the phase margin 125 begins to increase due to the introduction of a zero Z1 at zero frequency fz1-t. Because of the relatively large ESR Resr of a Tantalum capacitor, zero frequency fz1-t is relatively close to pole frequency fp1. If we assume output capacitor C1 is a Tantalum capacitor of 40 uF, a typical ESR Resr is approximately 0.15 ohms. If we further assume inductance L1 is 47 uH, and utilizing equation 2, the zero frequency fz1-t is approximately equal to 26.5 KHz. Because the zero frequency fz1-t of the Tantalum capacitance is relatively close to the pole frequency fp1-t, zero Z1 compensates for pole P1 and maintains a sufficient phase margin 125 to ensure a stable output. Thus, the Tantalum capacitor compensates for the pole P1 and shifts phase 123 back to a more stable region, resulting in a more stable output with reduced oscillation and noise.
FIGS. 3A and 3B show Bode plots of the response of output stage 120, where a ceramic capacitor is used in output stage 120 for capacitor C1. As was the case with the Tantalum capacitor, pole P1 causes an initial drop in both gain 122 and phase 123. However, unlike the phase resulting from the Tantalum capacitor as shown in FIG. 2B, phase 123 does not begin to ramp up to compensate for pole P1 because zero frequency fz1-c of zero Z1 for ceramic capacitance C1 is significantly greater than zero frequency fz1-t for Tantalum capacitor. This results in substantially a zero phase margin 125 (less than 5xc2x0) causing oscillation in output signal 126. The low phase margin 125 and lack of compensation for the phase shift caused by the pole P1 is due to the significantly smaller ESR Resr of ceramic capacitors. If we assume capacitor C1 is a ceramic capacitor of 40 uF, a typical ESR Resr is approximately 0.005 ohms. If we further assume inductance L1 is 47 uH, then, utilizing equation 2, the zero frequency fz1-c is approximately equal to 796 KHz, which is approximately 30 times the zero frequency fz1-t for the Tantalum capacitance. Because the zero Z1 occurs at a frequence which is significantly greater than the pole frequency fp1, and often greater than the operating frequency of the circuit utilizing filter 120, the phase margin 125 is substantially zero until zero Z1 begins to compensate for the pole P1. The relatively small or zero phase margin 125 results in an unstable output signal 126.
Therefore, Tantalum, aluminum electrolytic and other capacitors with larger ESR""s than ceramic capacitors have long been utilized in output circuits requiring a stabilized output signal 126, such as switching voltage regulators. However, the cost of these capacitors are substantially greater than the cost of ceramic capacitors thus greatly increasing the cost of manufacturing. Further, Tantalum capacitors are in extremely short supply. Thus the manufacturing of devices utilizing Tantalum capacitors may be drastically delayed because the Tantalum capacitors cannot be obtained, causing further increased costs.
In accordance with the teachings of this invention a novel method and apparatus is taught which provides for the stabilizing of an output signal through an output circuit having a compensation circuit coupled with an output capacitor, such that the compensation circuit is configured to compensate for an equivalent series resistance of the output capacitor. The compensation circuit compensates for the equivalent series resistance by providing a shift in a phase of the output signal to stabilize the output signal. The shift in phase is accomplished through the addition of a second zero at a second zero frequency to stabilize the output signal. The second zero is added such that the second zero frequency is closer to a first pole frequency than a first zero frequency, where the first zero frequency is proportional to the equivalent series resistance and the first pole is proportional to the output capacitor.
In one embodiment, the compensation circuit is configured to provide a shift in the phase of the output signal such that the output signal closely resemble a signal from an output stage having a Tantalum capacitor. In one embodiment, the output capacitor is a ceramic capacitor and the compensation circuit includes at least a compensation inductor and a compensation resistor.